An Open Chisel-Based Framework for Hardware Acceleration on High
: An open-source simulation and synthesis tool often used for quick functional checks. Migration & Limitations Migrating from ChiselTest | Chisel
ChiselSim is more than a simulation trick—it’s a philosophy: simulate where you design, with the tools you already know. By bringing simulation into the Chisel/Scala ecosystem, it eliminates context switching, accelerates debug cycles, and opens hardware design to modern software practices. For anyone serious about productive, testable, and maintainable digital design, ChiselSim is not just helpful—it’s essential. chiselsim
A typical testbench using ChiselSim involves the following actions: poke : Apply a value to a hardware input. peek : Read the current value of a hardware signal.
pieces to build a simulator rather than a complete one. This led to a shift toward providing a more complete, "out-of-the-box" simulation experience. Visualizing the Invisible: To help engineers "see" their circuits in action, hackers and contributors worked on ways to emit VCD files and generate waveforms, turning invisible digital logic into visual data. The Present: A Modern Toolchain Today, ChiselSim is a core component of the Chisel 7 release cycle. It is used in cutting-edge research, such as stream compressor generators and reconfigurable accelerators, providing the stimulus needed to verify the next generation of silicon. Would you like to see a An Open Chisel-Based Framework for Hardware Acceleration on
While powerful, ChiselSim has trade-offs:
The typical Chisel workflow involves generating Verilog, which is then passed to a third-party simulator. This introduces friction: the abstraction hierarchy is lost in translation to Verilog, and the engineer must rely on the simulator's specific API for testing. ChiselSim aims to close this loop by generating a simulator directly from the Chisel AST (Abstract Syntax Tree), allowing the testbench to remain in Scala and share data structures with the design. pieces to build a simulator rather than a complete one
: An open-source, high-performance Verilog/SystemVerilog simulator (recommended for most users). VCS : A commercial-grade functional simulator from Synopsys.
Traditional hardware description languages (HDLs) like Verilog and VHDL often suffer from the limitations of legacy syntax and vendor-specific tooling. Chisel addresses these by providing: