The System Power Management Interface (SPMI) is a high-speed, low-latency, two-wire serial bus designed by the MIPI Alliance . It serves as a hardware interface standard between the integrated Power Controller (PC) of a System-on-Chip (SoC) and one or more Power Management Integrated Circuits (PMICs).
These master and slave nodes can reside on a single integrated circuit, across separate discrete chips, or within a hybrid multi-chip module. Operating Speeds and Device Classes spmi bus
The SPMI bus protocol is a master-slave protocol, where a master device initiates transactions and a slave device responds to these transactions. The protocol consists of the following steps: The System Power Management Interface (SPMI) is a
While SPMI is mature (finalized ~2010, updated 2018), it remains the de facto standard for mobile and embedded power management. The MIPI Alliance continues to refine it with: Operating Speeds and Device Classes The SPMI bus
Embedded within auxiliary peripheral PMICs or custom voltage regulation subsystems.
The System Power Management Interface (SPMI) bus is a communication interface used in mobile devices, such as smartphones and tablets, to manage power consumption and system power management. It is a high-speed, low-power interface that allows different components of a system-on-chip (SoC) to communicate with each other and with external power management ICs.
A kernel driver can then: