The PCI Express (PCIe) Base Specification Revision 6.0 is a standard for high-speed interconnects used in computers and other electronic devices. The specification defines the architecture, protocol, and programming interface for PCIe, which is widely used for connecting peripherals, storage devices, and network interfaces to a computer's motherboard.
The link training and equalization process has been overhauled for PAM-4: pci express base specification revision 6.0
| Feature | PCIe 5.0 | PCIe 6.0 | | :--- | :--- | :--- | | | LFSR for 128b/130b | LFSR for FLITs | | Deskew | Across lanes using SKP OS | Across lanes using FLIT markers | | Clock Tolerance | ±300 ppm | ±300 ppm (same) | | Lane Polarity Inversion | Supported | Supported | | Low Power States | L0s, L1, L2 | L0s, L1, L2 (modified entry/exit) | The PCI Express (PCIe) Base Specification Revision 6
Because PAM-4 has higher inherent error rates (target Bit Error Rate after FEC: ≤ 10^-6, corrected to ≤ 10^-12), PCIe 6.0 mandates a mechanism: By doubling the data rate of PCIe 5
The headline feature of the PCIe 6.0 specification is its raw speed. By doubling the data rate of PCIe 5.0, it achieves: , up from 32 GT/s.