Pci Express Specification Jun 2026

The PCIe specification defines a layered architecture consisting of three distinct logical layers:

The upcoming PCI Express® (PCIe®) 6.0 specification will continue PCI-SIG's® longstanding history of innovation for the next gener... PCI-SIG Show all Specification Release Year Max Bandwidth (x16 Slot) Key Technology PCIe 3.0 2010 32 GB/s 128b/130b Encoding PCIe 4.0 2017 64 GB/s 16 GT/s per lane PCIe 5.0 2019 128 GB/s 32 GT/s per lane PCIe 6.0 2022 256 GB/s PAM4 Signaling, Flit Mode PCIe 7.0 2025 (Expected) 512 GB/s 128 GT/s; AI/ML focus PCIe 8.0 2028 (Target) 1,024 GB/s (1 TB/s) 256 GT/s; Optical awareness How It Works The specification defines several layers to ensure data reaches its destination reliably: Physical Layer pci express specification

PCIe 1.0 and 2.0 used 8b/10b encoding, meaning 2 bits of every 10 were overhead. PCIe 3.0 through 5.0 switched to 128b/130b, drastically reducing overhead. PCIe 6.0 introduced PAM-4 (Pulse Amplitude Modulation) signaling to double bandwidth once again. PCIe 6

While the standard PCIe slot remains ubiquitous, the specification has expanded to define numerous form factors. (for SSDs and Wi-Fi cards) and U.2 (for enterprise SSDs) are both PCIe-based, using the exact same protocol over different connectors. Thunderbolt 3 and 4 are essentially PCIe tunneling over a USB-C cable, allowing external graphics docks and storage to operate as if they were inside the chassis. Thunderbolt 3 and 4 are essentially PCIe tunneling